Vertical-Cavity Surface-Emitting Lasers (VCSELs) capable of high-power operation with precisely controlled transverse mode characteristics are becoming increasingly important in a variety of applications such as optical communications, position sensors, printing, and magnetic storage. In optical communications applications, differences in rise and fall times associated with specific spatial modes can lead to deterministic jitter. This problem can be exacerbated when VCSELs are coupled into multimode fibers, where differential mode delay (DMD) is also present. These factors can limit link speed and distance in data centers and enterprise networks.
A technique that has been used for mode suppression in VCSELs has been a surface relief method (or inverted surface relief method depending on the location of the etching). In the surface relief method, a layer of GaAs is grown on top of a regular VCSEL epitaxial structure. By itself the extra GaAs layer serves as an anti-phase layer when viewed from the cavity, which means that it perturbs the standing wave at both the top-DBR/GaAs interface and GaAs/air interface. This perturbation results in destructive interference for any portion of the standing wave of a transverse mode that impinges on the GaAs, increasing the cavity loss for said mode. There are inherent problems with using an extra GaAs layer as the phase-mismatch layer. The first is that the GaAs layer is produced in the epitaxial growth process as part of the VCSEL device structure. This means that the VCSEL layer structure must be used for this mode-suppression application only, as it has been designed to suppress lasing if not modified in the fabrication process. If part of the top GaAs layer is not removed, the entire laser will be affected by the anti-phase reflection and lasing will be suppressed. The second problem arises during the desired patterning and removal of specific portions of the GaAs anti-phase layer. Since it is desired that the fundamental mode be as unperturbed as possible, the centermost portion of the VCSEL anti-phase layer must be removed. However, this requires a very precise etch with limited options that would be acceptable for volume production. One possible method is via a wet chemical etch. However, since it is not practical to include an etch-stop below the anti-phase GaAs layer, a rigorously controlled process must be developed, and any deviation from the desired time, temperature, or chemical composition of the wet etch could ruin the VCSEL. The second possible method is via Ar-ion (or other heavy-ion) milling. This technique, though very precise in the etch depths that it can achieve, can cause significant damage to the top reflector DBR stack of the sample, leading to undesirable increases in defect density, scattering sites, or absorption loss, decreasing the performance of the VCSEL. Ion milling is generally not considered an acceptable wafer processing method, but does have utility for diagnostics.
Another technique for mode-suppression in VCSELs utilizes DBR regrowth on top of a patterned surface, or a Buried-Tunnel-Junction (BTJ), to achieve the phase-mismatch condition. These methods of regrowth utilize the same phase mismatch phenomenon as the surface relief technique and the proposed amorphous silicon thin film deposition, yet they require much more precise methods of fabrication that must occur during the middle of the layer structure growth itself. Growth is halted, typically after the first pair of the p-type top DBR is grown, and an extra, phase-mismatch layer is grown (either the BTJ layer or an extra half-pair of DBR). The sample is then removed from the growth chamber, patterned and etched to produce the desired structure (typically a disk or donut), then cleaned thoroughly and placed back into the chamber to resume growth.